Suresh Sitaraman

Professor; Director, Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab.

Dr. Sitaraman began at Tech in 1995 as an Assistant Professor. Prior, he was at IBM Corporation. Dr. Sitaraman's research is in the areas of micro- and nano-scale structure fabrication, characterization, physics-based modeling and reliable design. His micro- and nano-scale research focuses on a wide range of application areas such as aerospace and defense, automotive, computers and telecommunications, portable electronics, and medical. In particular, his research is developing micro-scale and nano-scale structures that can be used as compliant packaging interconnects. Such interconnects can also be used as bio-assays for cancer diagnosis and to determine the efficacy of cancer treatment. His research is also developing innovative stressed super layer techniques to determine the interfacial strength of thin structures ranging from 5 nm to 1-2 um. Dr. Sitaraman's research also aims to understand the long-term reliability of lead-based and lead-free solder interconnects through thermo-mechanical modeling, material microstructure evolution, reliability experiments, and laser moire interferometry. In parallel, Dr. Sitaraman's research focuses on the next-generation integrated substrates that have high-density interconnects and microvias, embedded passives, and optoelectronic waveguides. In particular, Dr. Sitarman's group has done work in material length scale effects for microvia reliability, cure kinetics and interlayer dielectric cracking and delamination, reliability modeling and experiments for embedded passives and optical waveguides.